The present disclosure relates to methods of curing underfill material, and particularly to methods of curing underfill material between a semiconductor chip and a substrate under a pressurized condition.
A semiconductor chip can be bonded to another semiconductor chip or a packaging substrate by employing Controlled Collapse Chip Connection (C4) process. Each C4 ball contacts a C4 pad on the semiconductor chip and another C4 pad on the other semiconductor chip or the packaging substrate. Each C4 pad is a contiguous metal pad typically formed out of the last metal layer of a metal interconnect structure during a semiconductor manufacturing sequence. Each C4 pad is large enough to accommodate the bottom portion of a C4 ball. Typically, an array of C4 balls can be employed to provide input/output (I/O) connections between the semiconductor chip and another semiconductor chip or a packaging substrate.
The C4 connections are susceptible to mechanical stress created by a mismatch in the coefficients of thermal expansion (CTE's) between the semiconductor chip and the other semiconductor chip or the packaging substrate. Such mechanical stress may cause cracks in the C4 balls or the semiconductor chip, causing the semiconductor chip to fail during usage. An underfill material, which easily deforms under stress, i.e., has a low value of Young's modulus, is employed to fill the space around the array of the C4 balls between the semiconductor chip and the other semiconductor chip or the packaging substrate. The underfill material absorbs the stress during the thermal expansion or contraction of the semiconductor chip, the array of C4 balls, and the other semiconductor chip or the packaging substrate, thereby preventing cracks in the bonded structure. In order to distribute the stress uniformly, however, it is necessary to have a uniform distribution of the underfill material without voids therein.
Recently, processes that apply the underfill material on a semiconductor chip or on a packaging substrate have been proposed. These processes enable filling spaces between an array of C4 balls with fewer and/or smaller cavities by applying the underfill material either on the substrate to which C4 balls are attached or to the other substrate to which C4 balls are not attached at the beginning of the bonding process. See, for example, U.S. Pat. No. 6,746,896 to Shi et al. and U.S. Pat. No. 6,902,954 to Shi.
One method is commonly referred to as the No Flow Underfill (NFU) method, in which the underfill material is pre-applied to a substrate. The other method is commonly referred to as the Wafer Level Underfill (WLU) method, in which the underfill material is pre-applied to a wafer, i.e., at least one semiconductor chip on a wafer. According to both methods, the pre-applied underfill material is cured in order to minimize the stress on low-k material layers in the semiconductor chip(s) during the flip chip assembly.
The pre-applied underfill material contains a fluxing component or flux capability in itself, and is subjected to the solder temperature, which is above the melting temperature of the solder material. For example, the melting temperature of lead-free solder is about 217° C. The relatively high soldering temperature causes large amounts of voids to form within the underfill material. The voids remain entrapped between the chip bumps on the semiconductor chip and the substrate bumps (or pads) on the substrate. The voids entrapped inside the underfill material are considered as a failure factor for the flip chip process because the areas including the voids do not absorb the mechanical stress. Further, some underfill material can be entrapped between a solder ball and a chip bump or a substrate bump, causing an electrical open.
On one hand, a low rate of temperature ramping can trigger an early cure of the underfill material, which minimizes formation of voids at the expense of maximizing entrapped underfill material between solder balls and the chip bumps or the substrate bumps during a flip chip bonding process. On the other hand, a high rate of temperature ramping can trigger a delayed cure of the underfill material, which minimizes formation of entrapped underfill materials between solder balls and the chip bumps or the substrate bumps voids at the expense of maximizing formation of voids due to aggressive reaction of underfill material during a flip chip bonding process. To date, a solution that reduces formation of entrapped underfill material on chip bumps or substrate bumps while reducing formation of voids in the underfill material has not been provided in the art.